A wide range of memory configurations exist in today's high-speed digital systems to meet platform-specific bandwidth, power, capacity, and cost constraints. For example, DDR4 (Double Data Rate IV) and GDDR5 (Graphics Double Data Rate V) based transceivers are expected to meet the needs of server, client, graphics, and mobile platforms. I/O (input-output) interfaces may need additional area and circuits to support bidirectional data transmission in combination with unidirectional data transmission.
For example, current DDR I/O drivers are primarily implemented as unidirectional push/pull devices with passive linearizing resistors. Due to passive resistor variation and low resistance density, the passive linearizing resistors increase significant area, pad capacitance, and metal routing complexity for the DDR I/O drivers. Supply regulation of a voltage-mode driver relies on certain amount of on-die de-coupling capacitors. This also takes up significant area. To support various I/O standards including unidirectional and bidirectional I/O interfaces using the same I/O driver may result in a large and complex design.